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DAC
2003
ACM
14 years 9 months ago
Scalable modeling and optimization of mode transitions based on decoupled power management architecture
To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact wi...
Dexin Li, Qiang Xie, Pai H. Chou
CODES
2009
IEEE
13 years 9 months ago
A scalable parallel H.264 decoder on the cell broadband engine architecture
The H.264 video codec provides exceptional video compression while imposing dramatic increases in computational complexity over previous standards. While exploiting parallelism in...
Michael A. Baker, Pravin Dalale, Karam S. Chatha, ...
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 3 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
ERSA
2007
194views Hardware» more  ERSA 2007»
13 years 10 months ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...
ICMCS
2006
IEEE
146views Multimedia» more  ICMCS 2006»
14 years 2 months ago
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-He...