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HPCA
2003
IEEE
14 years 8 months ago
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 12 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
IPSN
2007
Springer
14 years 1 months ago
Dozer: ultra-low power data gathering in sensor networks
Environmental monitoring is one of the driving applications in the domain of sensor networks. The lifetime of such systems is envisioned to exceed several years. To achieve this l...
Nicolas Burri, Pascal von Rickenbach, Roger Watten...
CGO
2006
IEEE
14 years 1 months ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 1 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen