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» Hardware Acceleration of HMMER on FPGAs
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EDBT
2010
ACM
133views Database» more  EDBT 2010»
14 years 2 months ago
FPGAs: a new point in the database design space
In line with the insight that “one size” of databases will not fit all application needs [19], the database community is currently exploring various alternatives to commodity...
René Müller, Jens Teubner
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 4 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
TVLSI
2008
115views more  TVLSI 2008»
13 years 7 months ago
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
13 years 11 months ago
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
Dirk Koch, Christian Haubelt, Jürgen Teich
IESS
2007
Springer
116views Hardware» more  IESS 2007»
14 years 2 months ago
Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes
This work investigates the use of reconfigurable devices as computing platform for self-organizing embedded systems. Those usually consist of a set of distributed, autonomous node...
Dominik Murr, Felix Mühlbauer, Falko Dressler...