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» Hardware Acceleration of HMMER on FPGAs
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FCCM
2006
IEEE
107views VLSI» more  FCCM 2006»
14 years 1 months ago
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
Uday Bondhugula, Ananth Devulapalli, James Dinan, ...
ENGL
2008
186views more  ENGL 2008»
13 years 8 months ago
High Performance Monte-Carlo Based Option Pricing on FPGAs
High performance computing is becoming increasingly important in the field of financial computing, as the complexity of financial models continues to increase. Many of these financ...
Xiang Tian, Khaled Benkrid, Xiaochen Gu
ICCD
1994
IEEE
157views Hardware» more  ICCD 1994»
14 years 10 hour ago
Mesh Routing Topologies for Multi-FPGA Systems
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a sy...
Scott Hauck, Gaetano Borriello, Carl Ebeling
FPL
2009
Springer
132views Hardware» more  FPL 2009»
13 years 11 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
CODES
2008
IEEE
14 years 2 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid