Sciweavers

112 search results - page 11 / 23
» Hardware Acceleration of Matrix Multiplication on a Xilinx F...
Sort
View
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 4 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 27 days ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
ERSA
2010
199views Hardware» more  ERSA 2010»
13 years 5 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
ERSA
2006
115views Hardware» more  ERSA 2006»
13 years 9 months ago
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation
Acoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo controller is its capability to hand...
Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven ...
ASAP
2007
IEEE
157views Hardware» more  ASAP 2007»
13 years 11 months ago
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations
Monte-Carlo simulations are used in many applications, such as option pricing and portfolio evaluation. Due to their high computational load and intrinsic parallelism, they are id...
David B. Thomas, Jacob A. Bower, Wayne Luk