112 search results - page 21 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
FCCM
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
GLVLSI
2009
IEEE
2009
IEEE
Physical unclonable function and true random number generator: a compact and scalable implementation
13 years 11 months ago
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
ICPADS
2006
IEEE
14 years 1 months ago
2006
IEEE
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
COMPSYSTECH
2009
13 years 5 months ago
2009
: This paper reveals the evolution of the polymorphic architectures in the context of ever increasing computational demands of the user applications and the need for formal archite...