112 search results - page 4 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
ARC
2010
Springer
14 years 2 months ago
2010
Springer
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
X-ray computed tomography (CT) images could be improved using iterative image reconstruction if the 3D conebeam forward- and back-projection computations can be accelerated signif...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...