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» Hardware Architecture of a Parallel Pattern Matching Engine
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ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
14 years 3 days ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
DAGSTUHL
2010
13 years 10 months ago
Visual Simulation of Flow
We have adopted a numerical method from computational fluid dynamics, the Lattice Boltzmann Method (LBM), for real-time simulation and visualization of flow and amorphous phenomen...
Arie E. Kaufman, Ye Zhao
IWOMP
2007
Springer
14 years 2 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...
CODES
2009
IEEE
14 years 1 months ago
A tuneable software cache coherence protocol for heterogeneous MPSoCs
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...
Frank E. B. Ophelders, Marco Bekooij, Henk Corpora...
COORDINATION
2009
Springer
14 years 9 months ago
Enhanced Coordination in Sensor Networks through Flexible Service Provisioning
: Heterogeneous wireless sensor networks represent a challenging programming environment. Servilla addresses this by offering a new middleware framework that provides service provi...
Chien-Liang Fok, Gruia-Catalin Roman, Chenyang Lu