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IPPS
2003
IEEE
14 years 1 months ago
Performance and Overhead in a Hybrid Reconfigurable Computer
In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. IntelÂ...
Osman Devrim Fidanci, Daniel S. Poznanovic, Kris G...
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
14 years 3 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
CEC
2010
IEEE
13 years 9 months ago
SBArt4 - Breeding abstract animations in realtime
Breeding Abstract Animations in Realtime Tatsuo Unemi SBART was developed in early 1990's as one of the derivatives from Artificial Evolution by Karl Sims. It has a functional...
Tatsuo Unemi
PACS
2000
Springer
110views Hardware» more  PACS 2000»
14 years 3 days ago
Compiler-Directed Dynamic Frequency and Voltage Scheduling
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies...
Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao
CDES
2006
184views Hardware» more  CDES 2006»
13 years 10 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way