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WSCG
2003
177views more  WSCG 2003»
13 years 10 months ago
An Architecture for Hierarchical Collision Detection
We present novel algorithms for efficient hierarchical collision detection and propose a hardware architecture for a single-chip accelerator. We use a hierarchy of bounding volum...
Gabriel Zachmann, Günter Knittel
FCCM
2007
IEEE
100views VLSI» more  FCCM 2007»
14 years 3 months ago
A Library and Platform for FPGA Bitstream Manipulation
— Since 1998, no commercially available FPGA has been accompanied by public documentation of its native machine code (or bitstream) format. Consequently, research in reconfigura...
Adam Megacz
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 3 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
COMPSAC
2005
IEEE
14 years 2 months ago
Preventing Illegal Usage of Mobile Phone Software
Mobile software industry is suffering from the illegal usage of the software. PKI will not be a solution for small software distribution. We introduce a lightweight but safe metho...
Yun-Sam Kim, Eun-Sun Cho
VEE
2005
ACM
199views Virtualization» more  VEE 2005»
14 years 2 months ago
Escape analysis in the context of dynamic compilation and deoptimization
In object-oriented programming languages, an object is said to escape the method or thread in which it was created if it can also be accessed by other methods or threads. Knowing ...
Thomas Kotzmann, Hanspeter Mössenböck