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ISCA
1990
IEEE
186views Hardware» more  ISCA 1990»
14 years 1 months ago
Adaptive Software Cache Management for Distributed Shared Memory Architectures
An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shar...
John K. Bennett, John B. Carter, Willy Zwaenepoel
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
14 years 1 months ago
Synthesis-for-testability using transformations
- We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and ...
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Skew scheduling and clock routing for improved tolerance to process variations
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
ICCAD
1997
IEEE
106views Hardware» more  ICCAD 1997»
14 years 1 months ago
BIST TPG for faults in system backplanes
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
Chen-Huan Chiang, Sandeep K. Gupta
ICFP
2002
ACM
14 years 9 months ago
Compiling scheme to JVM bytecode: : a performance study
We have added a Java virtual machine (henceforth JVM) bytecode generator to the optimizing Scheme-to-C compiler Bigloo. We named this new compiler BiglooJVM. We have used this new...
Bernard P. Serpette, Manuel Serrano