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» Hardware Reuse at the Behavioral Level
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ASPDAC
1995
ACM
79views Hardware» more  ASPDAC 1995»
14 years 19 hour ago
Search space reduction in high level synthesis by use of an initial circuit
Most existing high-level synthesis(HLS) systems attempt to generate a circuit from a behavioral description \out of the void", using the entire design space as the search dom...
Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, M...
MSE
2003
IEEE
92views Hardware» more  MSE 2003»
14 years 1 months ago
On simulating the IP Market Dynamics in an Academic Environment Using SystemC
As SoC (System-on-a-chip) methodology emerges, IP (Intellectual Property) development and integration will play a major role in the hightech industry. To prepare for this future t...
Ghaiyyur Quraishi, Ravi Shankar
WSC
2004
13 years 9 months ago
Implementing the High Level Architecture in the Virtual Test Bed
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
José A. Sepúlveda, Luis C. Rabelo, J...
PPOPP
1990
ACM
14 years 15 days ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
ICCBR
2007
Springer
14 years 2 months ago
Case-Based Planning and Execution for Real-Time Strategy Games
Abstract. Artificial Intelligence techniques have been successfully applied to several computer games. However in some kinds of computer games, like real-time strategy (RTS) games...
Santiago Ontañón, Kinshuk Mishra, Ne...