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» Hardware Reuse at the Behavioral Level
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ASPDAC
1995
ACM
127views Hardware» more  ASPDAC 1995»
14 years 1 days ago
Reclocking for high-level synthesis
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran
PROCEDIA
2010
66views more  PROCEDIA 2010»
13 years 6 months ago
Parallel signal processing with S-Net
We argue that programming high-end stream-processing applications requires a form of coordination language that enables the designer to represent interactions between stream-proce...
Frank Penczek, Stephan Herhut, Clemens Grelck, Sve...
ECBS
2003
IEEE
115views Hardware» more  ECBS 2003»
14 years 1 months ago
Details of Formalized Relations in Feature Models Using OCL
System families are a form of high level reuse of development assets in a specific problem domain, by making use of commonalities and variabilities. To represent assets belonging ...
Detlef Streitferdt, Matthias Riebisch, Ilka Philip...
MSE
1999
IEEE
118views Hardware» more  MSE 1999»
14 years 23 days ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
ICECCS
1998
IEEE
123views Hardware» more  ICECCS 1998»
14 years 22 days ago
Applying Slicing Technique to Software Architectures
Software architecture is receiving increasingly attention as a critical design level for software systems. As software architecture design resources (in the form of architectural ...
Jianjun Zhao