398 search results - page 39 / 80 » Hardware Reuse at the Behavioral Level |
139
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DAC
2006
ACM
15 years 10 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
138
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RTSS
2007
IEEE
15 years 10 months ago
2007
IEEE
The integration phase of real-time COTS-based systems is often problematic because when multiple tasks run concurrently, the interference at the bus level between cache fetching a...
148
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CODES
2006
IEEE
15 years 10 months ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
118
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ASPDAC
2006
ACM
15 years 10 months ago
2006
ACM
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...
120
Voted
SIGPLAN
2008
15 years 4 months ago
2008
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...