398 search results - page 39 / 80 » Hardware Reuse at the Behavioral Level |
DAC
2006
ACM
14 years 2 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
RTSS
2007
IEEE
14 years 2 months ago
2007
IEEE
The integration phase of real-time COTS-based systems is often problematic because when multiple tasks run concurrently, the interference at the bus level between cache fetching a...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...
SIGPLAN
2008
13 years 8 months ago
2008
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...