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» Hardware Reuse at the Behavioral Level
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ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
13 years 11 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 19 days ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
ECBS
2007
IEEE
188views Hardware» more  ECBS 2007»
13 years 9 months ago
Behavior Analysis-Based Learning Framework for Host Level Intrusion Detection
Machine learning has great utility within the context of network intrusion detection systems. In this paper, a behavior analysis-based learning framework for host level network in...
Haiyan Qiao, Jianfeng Peng, Chuan Feng, Jerzy W. R...
EH
2004
IEEE
118views Hardware» more  EH 2004»
13 years 11 months ago
Exploring Knowledge Schemes for Efficient Evolution of Hardware
There exist several approaches to improve the quality of evolution. In this paper, a priori design knowledge as a part of evolving systems is discussed. Further, experiments are r...
Jim Torresen
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
13 years 11 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...