103 search results - page 16 / 21 » Hardware Software Co-Design for Matrix Computations on Recon... |
CGO
2005
IEEE
14 years 21 days ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
ARC
2010
Springer
13 years 7 months ago
2010
Springer
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
FCCM
2004
IEEE
13 years 10 months ago
2004
IEEE
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—Accurate analog models of power system components are required in order to realize an analog computation engine for power systems. Analog computation is an area of continued int...
FCCM
2000
IEEE
13 years 11 months ago
2000
IEEE
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...