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DATE
2004
IEEE
114views Hardware» more  DATE 2004»
13 years 11 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
CAV
2007
Springer
120views Hardware» more  CAV 2007»
14 years 1 months ago
Using Counterexamples for Improving the Precision of Reachability Computation with Polyhedra
Abstract. We present an extrapolation with care set operator to accelerate termination of reachability computation with polyhedra. At the same time, a counterexample guided refine...
Chao Wang, Zijiang Yang, Aarti Gupta, Franjo Ivanc...
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
CGO
2007
IEEE
14 years 1 months ago
Evaluating Heuristic Optimization Phase Order Search Algorithms
Program-specific or function-specific optimization phase sequences are universally accepted to achieve better overall performance than any fixed optimization phase ordering. A ...
Prasad Kulkarni, David B. Whalley, Gary S. Tyson
CASES
2003
ACM
14 years 22 days ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid