Sciweavers

230 search results - page 11 / 46
» Hardware Support for Control Transfers in Code Caches
Sort
View
CODES
2008
IEEE
14 years 2 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
ICPP
2003
IEEE
14 years 23 days ago
Enabling Partial Cache Line Prefetching Through Data Compression
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
Youtao Zhang, Rajiv Gupta
HOST
2011
IEEE
12 years 7 months ago
Enhancing security via provably trustworthy hardware intellectual property
—We introduce a novel hardware intellectual property acquisition protocol, show how it can support the transfer of provably trustworthy modules between hardware IP producers and ...
Eric Love, Yier Jin, Yiorgos Makris
IEEEPACT
2002
IEEE
14 years 13 days ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
SIGMETRICS
2004
ACM
115views Hardware» more  SIGMETRICS 2004»
14 years 28 days ago
Emulating low-priority transport at the application layer: a background transfer service
Low priority data transfer across the wide area is useful in several contexts, for example for the dissemination of large files such as OS updates, content distribution or prefet...
Peter B. Key, Laurent Massoulié, Bing Wang