230 search results - page 12 / 46 » Hardware Support for Control Transfers in Code Caches |
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Memorylatency isbecominganincreasingly importantperformance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we sw...
IOPADS
1996
13 years 8 months ago
1996
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
CODES
2011
IEEE
12 years 7 months ago
2011
IEEE
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for tr...
RSP
2000
IEEE
13 years 12 months ago
2000
IEEE
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...