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» Hardware Support for Control Transfers in Code Caches
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CF
2006
ACM
14 years 1 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
13 years 11 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
ICS
2003
Tsinghua U.
14 years 22 days ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
FPL
2007
Springer
124views Hardware» more  FPL 2007»
14 years 1 months ago
A Quantitative Prediction Model for Hardware/Software Partitioning
An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spo...
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Ga...
IWMM
2009
Springer
114views Hardware» more  IWMM 2009»
14 years 2 months ago
Scalable support for multithreaded applications on dynamic binary instrumentation systems
Dynamic binary instrumentation systems are used to inject or modify arbitrary instructions in existing binary applications; several such systems have been developed over the past ...
Kim M. Hazelwood, Greg Lueck, Robert Cohn