230 search results - page 17 / 46 » Hardware Support for Control Transfers in Code Caches |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Hardware transactional memory has great potential to simplify the creation of correct and efficient multithreaded programs, allowing programmers to exploit more effectively the s...
IEEEPACT
2003
IEEE
14 years 24 days ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
USENIX
2003
13 years 9 months ago
2003
This paper presents a new asynchronous programming library (libasync-smp) that allows event-driven applications to take advantage of multiprocessors by running code for event hand...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...