230 search results - page 18 / 46 » Hardware Support for Control Transfers in Code Caches |
ISCA
2010
IEEE
14 years 19 days ago
2010
IEEE
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
CF
2010
ACM
14 years 18 days ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
CODES
2003
IEEE
14 years 25 days ago
2003
IEEE
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed arc...