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» Hardware Support for Priority Inheritance
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CODES
2003
IEEE
14 years 2 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
IESS
2007
Springer
156views Hardware» more  IESS 2007»
14 years 2 months ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
Jelena Trajkovic, Daniel Gajski
INFOCOM
2010
IEEE
13 years 7 months ago
Scalable Modulation for Scalable Wireless Videocast
Abstract— In conventional wireless systems with layered architectures, the physical layer treats all data streams from upper layers equally and apply the same modulation and codi...
Lin Cai, Yuanqian Luo, Siyuan Xiang, Jianping Pan
RTSS
2006
IEEE
14 years 2 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
TVCG
2012
195views Hardware» more  TVCG 2012»
11 years 11 months ago
Restricted Trivariate Polycube Splines for Volumetric Data Modeling
—This paper presents a volumetric modeling framework to construct a novel spline scheme called restricted trivariate polycube splines (RTP-splines). The RTP-spline aims to genera...
Kexiang Wang, Xin Li, Bo Li 0014, Huanhuan Xu, Hon...