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144
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MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
15 years 1 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
134
Voted
ISCAS
1999
IEEE
87views Hardware» more  ISCAS 1999»
15 years 8 months ago
Instruction level power model of microcontrollers
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...
C. Chakrabarti, D. Gaitonde
140
Voted
SIPS
2006
IEEE
15 years 9 months ago
Automated Architectural Exploration for Signal Processing Algorithms
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winse...
124
Voted
JORS
2010
149views more  JORS 2010»
14 years 10 months ago
Modelling LGD for unsecured personal loans: decision tree approach
The Basel New Accord which is being implemented throughout the banking world on 1 January 2007 has made a significant difference to the use of modelling within financial organisat...
Ania Matuszyk, C. Mues, Lyn C. Thomas
110
Voted
IROS
2006
IEEE
120views Robotics» more  IROS 2006»
15 years 9 months ago
3D Pose Visual Servoing Relieves Parallel Robot Control from Joint Sensing
— In this paper, we show that visual feedback reduces the complexity of parallel robot Cartesian control. Namely, 3D pose visual servoing, where the end-effector pose is indirect...
Tej Dallej, Nicolas Andreff, Youcef Mezouar, Phili...