3902 search results - page 169 / 781 » Hardware Synthesis from C C Models |
142
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AHS
2007
IEEE
15 years 7 months ago
2007
IEEE
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
119
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WSC
2001
15 years 5 months ago
2001
In models of military operations it is important to include the Command and Control (C2) process in order to achieve a realistic simulation of a military force's behaviour an...
113
Voted
ASYNC
2004
IEEE
15 years 7 months ago
2004
IEEE
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
131
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ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
Abstract— A complexity model for context-based adaptive variable length coding (CAVLC) and universal variable length coding (UVLC) in the H.264/AVC decoder is proposed. CAVLC and...
145
Voted
ISLPED
2005
ACM
15 years 9 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...