Sciweavers

3902 search results - page 180 / 781
» Hardware Synthesis from C C Models
Sort
View
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
15 years 9 months ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
112
Voted
DATE
2000
IEEE
85views Hardware» more  DATE 2000»
15 years 8 months ago
Gate Sizing Using a Statistical Delay Model
This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used al...
E. T. A. F. Jacobs, Michel R. C. M. Berkelaar
IPPS
2003
IEEE
15 years 9 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...
ECBS
2007
IEEE
149views Hardware» more  ECBS 2007»
15 years 10 months ago
Component-Based System Integration via (Meta)Model Composition
This paper provides three contributions to the study of functional integration of distributed enterprise systems. First, we describe the challenges associated with functionally in...
Krishnakumar Balasubramanian, Douglas C. Schmidt, ...
ISLPED
2010
ACM
205views Hardware» more  ISLPED 2010»
15 years 4 months ago
Peak power modeling for data center servers with switched-mode power supplies
Accurately modeling server power consumption is critical in designing data center power provisioning infrastructure. However, to date, most research proposals have used average CP...
David Meisner, Thomas F. Wenisch