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ASPDAC
2006
ACM
131views Hardware» more  ASPDAC 2006»
14 years 3 months ago
POSIX modeling in SystemC
- Early estimation of the execution time of Real-Time embedded SW is an essential task in complex, HW/SW embedded system design. Application SW execution time estimation requires t...
Hector Posadas, Jesús Ádamez, Pablo ...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 3 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
14 years 1 months ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 3 months ago
Overcoming limitations of the SystemC data introspection
—Today verification, testing and debugging of SystemC models can be applied at an early stage in the design process. To support these techniques gaining required information of ...
Christian Genz, Rolf Drechsler
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
14 years 3 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind