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ASAP
2010
IEEE
127views Hardware» more  ASAP 2010»
13 years 11 months ago
Design of throughput-optimized arrays from recurrence abstractions
urrence abstractions Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Design of ut-optimized arrays from rec...
Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chambe...
ENTCS
2010
113views more  ENTCS 2010»
13 years 10 months ago
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
Dan R. Ghica, Alex Smith
CODES
2006
IEEE
14 years 4 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
CODES
2005
IEEE
14 years 3 months ago
Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems
Scripting is a powerful, high-level, cross-platform, dynamic, easy way of composing software modules as black boxes. Unfortunately, the high runtime overhead has prevented scripti...
Jiwon Hahn, Qiang Xie, Pai H. Chou
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
14 years 4 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...