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» Hardware Synthesis from Term Rewriting Systems
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PC
2007
343views Management» more  PC 2007»
13 years 9 months ago
Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexa...
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
14 years 10 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
SIGCOMM
2009
ACM
14 years 4 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy
SBCCI
2005
ACM
98views VLSI» more  SBCCI 2005»
14 years 3 months ago
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy c...
José Carlos S. Palma, César A. M. Ma...
FTDCS
2004
IEEE
14 years 1 months ago
The vMatrix: Server Switching
Today most Internet services are pre-assigned to servers statically, hence preventing us from doing real-time sharing of a pool of servers across as group of services with dynamic...
Amr Awadallah, Mendel Rosenblum