Sciweavers

974 search results - page 26 / 195
» Hardware Synthesis from Term Rewriting Systems
Sort
View
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 5 months ago
Scalable and scalably-verifiable sequential synthesis
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
Alan Mishchenko, Michael L. Case, Robert K. Brayto...
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
14 years 2 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...
IFIP
2004
Springer
14 years 2 months ago
Ensuring Termination by Typability
A term terminates if all its reduction sequences are of finite length. We show four type systems that ensure termination of well-typed π-calculus processes. The systems are obtai...
Yuxin Deng, Davide Sangiorgi
CODES
2007
IEEE
14 years 3 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
ASYNC
2001
IEEE
164views Hardware» more  ASYNC 2001»
14 years 14 days ago
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism
This paper describes the synthesis and hardware implementation of a signal-type asynchronous data communication mechanism (ACM). Such an ACM can be used in systems where a data-dr...
Alexandre Yakovlev, Fei Xia, Delong Shang