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» Hardware design experiences in ZebraNet
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ICCD
2000
IEEE
120views Hardware» more  ICCD 2000»
14 years 2 months ago
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Viresh Paruthi, Andreas Kuehlmann
DAC
2006
ACM
14 years 11 months ago
Games are up for DVFS
Graphics-intensive computer games are no longer restricted to highperformance desktops, but are also available on a variety of portable devices ranging from notebooks to PDAs and ...
Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi
SIGCOMM
2009
ACM
14 years 4 months ago
VL2: a scalable and flexible data center network
To be agile and cost effective, data centers should allow dynamic resource allocation across large server pools. In particular, the data center network should enable any server to...
Albert G. Greenberg, James R. Hamilton, Navendu Ja...
CODES
2007
IEEE
14 years 4 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 3 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...