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    CONEXT
    2008
    ACM
    163views Computer Networks» more  CONEXT 2008»
    TDM MAC protocol design and implementation for wireless mesh networks
    13 years 9 months ago
    TDM MAC protocol design and implementation for wireless mesh networks
    Download  web.ics.purdue.edu
    We present the design, implementation, and evaluation of a Time Division Multiplex (TDM) MAC protocol for multihop wireless mesh networks using a programmable wireless platform. E...
    Dimitrios Koutsonikolas, Theodoros Salonidis, Henr...
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    TJS
    2002
    118views more  TJS 2002»
    On the Design, Development, Deployment, and Network Survivability Analysis of the Dynamic Routing System Protocol
    13 years 7 months ago
    On the Design, Development, Deployment, and Network Survivability Analysis of the Dynamic Routing System Protocol
    Download  www.ir.iit.edu
    : With the ever-increasing demands on server applications, reliability is of paramount importance. Often these services are implemented using a distributed server cluster architect...
    Abdur Chowdhury, Ophir Frieder, Peng-Jun Wan
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    FPL
    2004
    Springer
    144views Hardware» more  FPL 2004»
    A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
    13 years 11 months ago
    A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
    Download  halcyon.usc.edu
    A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
    Jingzhao Ou, Viktor K. Prasanna
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    TCAD
    2008
    101views more  TCAD 2008»
    Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
    13 years 7 months ago
    Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
    Download  www.eecs.umich.edu
    Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
    Ilya Wagner, Valeria Bertacco, Todd M. Austin
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    ISCA
    2011
    IEEE
    313views Hardware» more  ISCA 2011»
    FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
    12 years 11 months ago
    FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
    Download  people.engr.ncsu.edu
    A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
    Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
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