951 search results - page 48 / 191 » Hardware design experiences in ZebraNet |
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
ICES
2003
Springer
14 years 27 days ago
2003
Springer
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
ISCAS
2003
IEEE
14 years 29 days ago
2003
IEEE
Abstract - A comprehensive study of ultra high-speed currentmode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically desi...
IROS
2006
IEEE
14 years 1 months ago
2006
IEEE
- This paper presents the design of an experimental system for assembly applications in space. The prototypical application is the assembly of mechanical trusses. The system used a...
AHS
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS...