951 search results - page 70 / 191 » Hardware design experiences in ZebraNet |
INFOCOM
2000
IEEE
14 years 2 months ago
2000
IEEE
Abstract— In this paper, we share our experience in designing and building a content based switch which we call L5. In addition to the layer 2-3-4 information available in the pa...
CASES
2010
ACM
13 years 8 months ago
2010
ACM
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
IEEEPACT
2005
IEEE
14 years 3 months ago
2005
IEEE
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
IEEEPACT
2003
IEEE
14 years 3 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...