Sciweavers

951 search results - page 79 / 191
» Hardware design experiences in ZebraNet
Sort
View
138
Voted
MICRO
2007
IEEE
113views Hardware» more  MICRO 2007»
15 years 4 months ago
The High Cost of a Cheap Lesson
y abstract, it is grounded in the experience of many markets. As I will illustrate, it explains much strategic behavior. Information spreads With a bit of effort, any technically s...
Shane Greenstein
122
Voted
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
16 years 1 months ago
An analytical model for negative bias temperature instability
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
CODES
2006
IEEE
15 years 10 months ago
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
Manjunath Kudlur, Kevin Fan, Scott A. Mahlke
DATE
2005
IEEE
91views Hardware» more  DATE 2005»
15 years 10 months ago
Reliability-Centric High-Level Synthesis
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density c...
Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, ...
114
Voted
ASPDAC
2006
ACM
134views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Constraint driven I/O planning and placement for chip-package co-design
System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional ma...
Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He