—We present a method for using programmable graphics hardware to solve a variety of boundary value problems. The time-evolution of such problems is frequently governed by partial...
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
We present a hardware-accelerated adaptive EWA volume splatting algorithm. EWA splatting combines a Gaussian reconstruction kernel with a low-pass image filter for high image qual...
Wei Chen, Liu Ren, Matthias Zwicker, Hanspeter Pfi...
Several secure computing hardware architectures using memory encryption and memory integrity checkers have been proposed during the past few years to provide applications with a t...
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...