421 search results - page 17 / 85 » Hardware efficient architectures for Eigenvalue computation |
EGH
2003
Springer
14 years 1 months ago
2003
Springer
—We present a method for using programmable graphics hardware to solve a variety of boundary value problems. The time-evolution of such problems is frequently governed by partial...
APCSAC
2001
IEEE
14 years 4 days ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
VIS
2004
IEEE
14 years 9 months ago
2004
IEEE
We present a hardware-accelerated adaptive EWA volume splatting algorithm. EWA splatting combines a Gaussian reconstruction kernel with a low-pass image filter for high image qual...
ACSAC
2006
IEEE
14 years 7 days ago
2006
IEEE
Several secure computing hardware architectures using memory encryption and memory integrity checkers have been proposed during the past few years to provide applications with a t...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...