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» Hardware efficient architectures for Eigenvalue computation
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DPHOTO
2010
176views Hardware» more  DPHOTO 2010»
13 years 10 months ago
Low-cost space-varying FIR filter architecture for computational imaging systems
Recent research demonstrates the advantage of designing electro-optical imaging systems by jointly optimizing the optical and digital subsystems. The optical systems designed usin...
Guotong Feng, Mohammed Shoaib, Edward L. Schwartz,...
IPPS
2005
IEEE
14 years 2 months ago
Embedded MPLS Architecture
This paper presents a hardware architecture for Multi Protocol Label Switching (MPLS). MPLS is a protocol used primarily to prioritize internet traffic and improve bandwidth utili...
Raymond Peterkin, Dan Ionescu
VIS
2006
IEEE
214views Visualization» more  VIS 2006»
14 years 9 months ago
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
Wei Qiao, Michael McLennan, Rick Kennell, David...
HPCA
2009
IEEE
14 years 9 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
TCOS
2010
13 years 3 months ago
Green Secure Processors: Towards Power-Efficient Secure Processor Design
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the softwar...
Siddhartha Chhabra, Yan Solihin