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» Hardware efficient architectures for Eigenvalue computation
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IPPS
2000
IEEE
13 years 11 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
ESANN
2006
13 years 8 months ago
FPGA implementation of an integrate-and-fire LEGION model for image segmentation
Abstract. Despite several previous studies, little progress has been made in building successful neural systems for image segmentation in digital hardware. Spiking neural networks ...
Bernard Girau, Cesar Torres-Huitzil
DAC
2009
ACM
14 years 8 months ago
Non-intrusive dynamic application profiling for multitasked applications
Application profiling ? the process of monitoring an application to determine the frequency of execution within specific regions ? is an essential step within the design process f...
Karthik Shankar, Roman L. Lysecky
DAC
2003
ACM
14 years 8 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
VLSID
2002
IEEE
123views VLSI» more  VLSID 2002»
14 years 7 months ago
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...