421 search results - page 79 / 85 » Hardware efficient architectures for Eigenvalue computation |
HPDC
2010
IEEE
13 years 7 months ago
2010
IEEE
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have ne...
ISCA
2012
IEEE
11 years 9 months ago
2012
IEEE
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...