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VLSID
2007
IEEE
100views VLSI» more  VLSID 2007»
14 years 8 months ago
Hardware Efficient Piecewise Linear Branch Predictor
Piecewise linear branch predictor has been demonstrated to have superior prediction accuracy; however, its huge hardware overhead prevents the predictor from being practical in the...
Jiajin Tu, Jian Chen, Lizy K. John
TC
2010
13 years 3 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
VLSISP
2010
148views more  VLSISP 2010»
13 years 6 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
DATE
2009
IEEE
242views Hardware» more  DATE 2009»
14 years 3 months ago
A high performance reconfigurable Motion Estimation hardware architecture
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilk...
CCS
2007
ACM
14 years 13 days ago
Reconfigurable trusted computing in hardware
Trusted Computing (TC) is an emerging technology towards building trustworthy computing platforms. The Trusted Computing Group (TCG) has proposed several specifications to impleme...
Thomas Eisenbarth, Tim Güneysu, Christof Paar...