355 search results - page 8 / 71 » Hardware implementation of a novel genetic algorithm |
ASYNC
2004
IEEE
13 years 11 months ago
2004
IEEE
One of the main reasons for using asynchronous design is that it offers the opportunity to exploit the datadependent latency of many operations in order to achieve low-power, high...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
GECCO
2008
Springer
13 years 8 months ago
2008
Springer
This paper describes initial testing of a novel idea to combine a CGP with an EDA. In recent work a new improved crossover technique was successfully applied to a CGP. To implemen...