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» Hardware scheduling support in SMP architectures
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CASES
2001
ACM
13 years 10 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...
SP
1999
IEEE
125views Security Privacy» more  SP 1999»
13 years 11 months ago
A Multi-Threading Architecture for Multilevel Secure Transaction Processing
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design ...
Haruna R. Isa, William R. Shockley, Cynthia E. Irv...
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
14 years 22 days ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
INFOCOM
1996
IEEE
13 years 11 months ago
Network Algorithms and Protocol for Multimedia Servers
In this paper, we present a network service specifically designed for multimedia servers. It uses a histogram based traffic characterization and an overload control protocol to el...
Pawan Goyal, Harrick M. Vin
CACM
2008
100views more  CACM 2008»
13 years 6 months ago
TxLinux and MetaTM: transactional memory and the operating system
TxLinux is the first operating system to use hardware transactional memory (HTM) as a synchronization primitive, and the first to manage HTM in the scheduler. TxLinux, which is a ...
Christopher J. Rossbach, Hany E. Ramadan, Owen S. ...