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ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 8 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
DATE
2011
IEEE
235views Hardware» more  DATE 2011»
12 years 11 months ago
An Overview of Approaches Towards the Timing Analysability of Parallel Architecture
In order to meet performance/low energy/integration requirements, parallel architectures (multithreaded cores and multi-cores) are more and more considered in the design of embedd...
Christine Rochange
CODES
2003
IEEE
14 years 1 months ago
Early estimation of the size of VHDL projects
The analysis of the amount of human resources required to complete a project is felt as a critical issue in any company of the electronics industry. In particular, early estimatin...
William Fornaciari, Fabio Salice, Daniele Paolo Sc...
ICESS
2007
Springer
14 years 1 months ago
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator
In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing thei...
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zaman...
CODES
2003
IEEE
14 years 1 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski