Early estimation of the size of VHDL projects

The analysis of the amount of human resources required to complete a project is felt as a critical issue in any company of the electronics industry. In particular, early estimating the effort involved in a development process is a key requirement for any cost-driven system-level design decision. In this paper, we present a methodology to predict the final size of a VHDL project on the basis of a high-level description, obtaining a significant indication about the development effort. The methodology is the composition of a number of specialized models, tailored to estimate the size of specific component types. Models were trained and tested on two disjoint and large sets of real VHDL projects. Quality-of-result indicators show that the methodology is both accurate and robust. Categories and Subject Descriptors B.6.3 [Hardware]: Design Aids—Hardware description languages; D.2.8 [Software Engineering]: Metrics—complexity measures General Terms Management, Design, Languages Keyword...

• Type: Conference
• Year: 2003
• Where: CODES
• Authors: William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza
• Keywords: CODES 2003, Hardware-Software Codesign, System-level Design, System-level Design Decision, Vhdl Projects