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» Hardware support for code integrity in embedded processors
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TVLSI
2008
108views more  TVLSI 2008»
13 years 7 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
CODES
2007
IEEE
14 years 1 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
CASES
2007
ACM
13 years 11 months ago
A fast and generic hybrid simulation approach using C virtual machine
Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to i...
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Asch...
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
13 years 11 months ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
CAV
2008
Springer
139views Hardware» more  CAV 2008»
13 years 9 months ago
CSIsat: Interpolation for LA+EUF
We present CSIsat, an interpolating decision procedure for the quantifier-free theory of rational linear arithmetic and equality with uninterpreted function symbols. Our implementa...
Dirk Beyer, Damien Zufferey, Rupak Majumdar