Sciweavers

71 search results - page 9 / 15
» Hardware-Supported Fault Tolerance for Multiprocessors
Sort
View
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
14 years 17 days ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
DSD
2011
IEEE
194views Hardware» more  DSD 2011»
12 years 7 months ago
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
SPAA
1997
ACM
13 years 12 months ago
Fine-Grain Multithreading with the EM-X Multiprocessor
- Multithreading aims to tolerate latency by overlapping communication with computation. This report explicates the multithreading capabilities of the EM-X distributed-memory multi...
Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato...
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
13 years 12 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
14 years 1 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar