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» Hazard Checking of Timed Asynchronous Circuits Revisited
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FORMATS
2006
Springer
13 years 11 months ago
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
Remy Chevallier, Emmanuelle Encrenaz-Tiphèn...
ACSD
2003
IEEE
91views Hardware» more  ACSD 2003»
14 years 28 days ago
A Polynomial-Time Algorithm for Checking Consistency of Free-Choice Signal Transition Graphs
Signal Transition Graphs (STGs) are one of the most popular models for the specification of asynchronous circuits. A STG can be implemented if it admits a so-called consistent an...
Javier Esparza
ASYNC
1997
IEEE
140views Hardware» more  ASYNC 1997»
13 years 11 months ago
The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
Kenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Pete...
MJ
2007
119views more  MJ 2007»
13 years 7 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...