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» Heterogeneous behavioral hierarchy for system level designs
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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 25 days ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
HPCA
2002
IEEE
14 years 8 months ago
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
Power dissipation has become one of the most critical factors for the continued development of both high-end and low-end computer systems. The successful design and evaluation of ...
Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary J...
CLUSTER
2009
IEEE
13 years 11 months ago
24/7 Characterization of petascale I/O workloads
Abstract--Developing and tuning computational science applications to run on extreme scale systems are increasingly complicated processes. Challenges such as managing memory access...
Philip H. Carns, Robert Latham, Robert B. Ross, Ka...
WISE
2002
Springer
14 years 15 days ago
UTML: Unified Transaction Modeling Language
Web transactions may be complex, composed of several sub-transactions accessing different resources including legacy systems. They may also have complex semantics. To deal with co...
Nektarios Gioldasis, Stavros Christodoulakis
UIST
1993
ACM
13 years 11 months ago
VB2: An Architecture for Interaction in Synthetic Worlds
This paper describes the VB2 architecture for the construction of three-dimensional interactive applications. The system's state and behavior are uniformly represented as a n...
Enrico Gobbetti, Jean-Francis Balaguer, Daniel Tha...