723 search results - page 128 / 145 » Heterogeneous behavioral hierarchy for system level designs |
CASES
2006
ACM
14 years 1 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
EUROSYS
2007
ACM
13 years 9 months ago
2007
ACM
Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While exist...
IJPP
2006
13 years 7 months ago
2006
Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, co...
ATAL
2005
Springer
14 years 1 months ago
2005
Springer
One aspect of rational behavior is that agents can pursue multiple goals in parallel. Current BDI theory and systems do not provide a theoretical or architectural framework for de...
CODES
2003
IEEE
14 years 24 days ago
2003
IEEE
Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time acc...