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» Heterogeneous behavioral hierarchy for system level designs
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CODES
2009
IEEE
13 years 11 months ago
Building heterogeneous reconfigurable systems with a hardware microkernel
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
Jason Agron, David L. Andrews
OTM
2004
Springer
14 years 26 days ago
Design a High-Level Language for Large Network Security Management
A common breach of network security is the class of attacks called Worm-virus. This paper proposes a language called Triton whose goal is to efficiently and effectively safeguard ...
Jangha Kim, Byungwook Song, Kanghee Lee, Sangwook ...
FPL
2001
Springer
96views Hardware» more  FPL 2001»
14 years 2 hour ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...
EMSOFT
2005
Springer
14 years 1 months ago
SHIM: a deterministic model for heterogeneous embedded systems
— Typical embedded hardware/software systems are implemented using a combination of C and an HDL such as Verilog. While each is well-behaved in isolation, combining the two gives...
Stephen A. Edwards, Olivier Tardieu
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
11 years 10 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...